Integrated circuits formed on semiconductor substrates typically include several metal layers that electrically interconnect the devices formed therein. The different metal layers are separated by insulating layers known as interlevel (or interlayer) dielectric layers (ILD) that have etched via holes (also known as vias) therein to connect devices or active regions from one layer of metal to the next.
Copper (Cu) interconnects are increasingly used for high density devices because of copper's improved conductivity relative to conventional materials such as aluminum (Al). The use of copper as the interconnect material presents various fabrication problems. First, there is currently no production-worthy etch process for copper. The damascene and dual damascene approaches have developed to address this shortcoming. A brief description of the dual damascene process is provided hereafter as described, for example, in U.S. Pat. No. 6,444,568 to Sundarararjan et al., entitled “Method of Forming Copper Diffusion Barrier”, the entirety of which is hereby incorporated herein by reference.
In the dual damascene process, an insulating layer is deposited over a copper layer. The insulating layer is then patterned to form a two-step connection having a narrower lower portion (referred to as a via portion) exposing selected connection areas on the underlying patterned metal layer and a wider upper portion (referred to as a trench portion) that serves to form the next layer of metal lines. The trench or the via portion can be formed first. Copper is then deposited to fill the two-step connection. A top portion of the copper layer is then removed using a chemical mechanical polishing (CMP) process. The resultant structure includes a via (the copper filled via portion) that connects the underlying metal layer with an overlying copper line (the copper filled trench portion). The contacts from the first copper metal layer to the devices are usually made with Tungsten (W) plugs.
When copper is used for these interconnects, the copper atoms must be prevented from migrating or diffusing into adjacent interlayer dielectric layers to prevent compromise of the integrity of the dielectric layers, particularly at low temperatures and under accelerated electric fields. Therefore, a dielectric diffusion barrier (DDB) is typically formed between the top of the copper metal line or layer and a subsequently deposited ILD to prevent this migration. Likewise, the copper metal line may be encapsulated with a diffusion barrier to prevent migration into a surrounding inter-metal dielectric (IMD) layer.
Currently, refractory metals such as Tantalum and Titanium and their nitrided compounds, i.e., TaN and TiN, are employed as the metal barrier against copper penetration into SiO2 and low-k interlayer dielectric layers. As device sizes decrease to 0.1 μm and below, however, the main advantage of using low-resistance copper interconnects begins to be negated by the higher resistance metal barrier layers, resulting in an increase in RC time delay. Still further, as these refractory metal barrier layers become increasingly thinner, reliability concerns such as line-line leakage, time-dependent dielectric breakdown (TDDB) lifetime and BTS (Bias-Temperature Stress) leakage arise due to poor barrier integrity.
Therefore, there remains a need for an improved low resistance copper interconnect structure and method of manufacturing the same in integrated circuit devices.